Computer architectures have entered a watershed as the quantity of network data generated by user applications exceed the data-processing capacity of any individual computer end-system. Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only. Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction. Performance evaluation is non-trivial to multiple aspects to such as picking workloads, selecting an appropriate modeling or simulation approach, running the model and interpreting the results using meaningful metrics. Performance data may drive research and development in a wrong direction. Design needs to reduce costs, save power and increase performance in a multi-scale approach that has potential application from nano scale to data-centre-scale computers.
Microprocessor, Cloud-Based Services, Networking and Computing, Computer Architecture
[1]
Cisco. 2014 Cisco global cloud index: forecast and methodology, 2013–2018.
[2]
Chen Y, Sion R. 2011 To cloud or not to cloud? musings on costs and viability. In Proc. ACMSymp. on Cloud Computing, Cascais, Portugal, 26–28 October 2011, pp. 29:1–29:7. New York.
[3]
Costa P, Ballani H, Narayanan D. 2014 Rethinking the network stack for rack-scale computers. In Proc. HotCloud, Philadelphia, PA, 17–18 June 2014. Berkeley, CA
[4]
Intel. 2014 Intel rack scale architecture: faster service delivery and lower TCO. May 2015.
[5]
Kyathsandra J, Dahlen E. 2013 Intel Rack Scale architecture overview. In Proc. INTEROP, LasVegas, NV, 2–6 May 2013. San Francisco, CA.
[6]
Falsafi B. 2015 Heterogeneous memory and its impact on rack-scale computing. In Proc. 2nd Int. Workshop on Rack-scale Computing, Bordeaux, France, 21 April 2015.
[7]
Moore GE. 1965 Cramming more components onto integrated circuits. Electronics 38, 114–117.
[8]
Patterson DA, Hennessy JL. 2013 Computer organization and design: the hardware/softwareinterface. London, UK.
[9]
Park C, Badeau R, Biro L, Chang J, Singh T, Vash J, Wang B, Wang T. Tbpsonchipring interconnect for 45 nm 8-core enterprise xeon processor. In Proc. IEEE Int. Solid-StateCircuits Conf., San Francisco, CA, 7–11 February 2010, pp. 180–181. Piscataway.
[10]
Gallenmüller S, Emmerich P, Wohlfart F, Raumer D, Carle G. Comparison of frameworks for high-performance packet IO. In Proc. ACM/IEEE Symp. on Architectures for networking and Communications Systems, Santa Clara, CA, 17–18 March 2016, pp. 29–38. New York.
[11]
Novakovi´c S, Daglis A, Bugnion E, Falsafi B, Grot B. In Proc. Int. Conf. on Architectural Support for Programming Languages and Operating Systems, Salt Lake City, UT,1–5 March 2014, pp. 3–18. New York.
[12]
Daglis A, Novakovic S, Bugnion E, Falsafi B, Grot B. 2015 Manycore network interfaces for in-memory rack-scale computing. In Proc. Int. Symp. in Computer Architecture, Portland, OR,13–17 June 2015. New York.
[13]
Zilberman N, Watts PM, Rotsos C, Moore AW. 2015 Reconfigurable network systems and software-defined networking. Proc. IEEE 103, 1102–1124.
[14]
Intel. 2014 Intel re-architects the fundamental building block for high-performance computing. Intelr%e-architects-the-fundamental-building-block-for-high-performance-computing (accessed January 2015).
[15]
Henning JL. 2006 SPEC CPU2006 benhmark descriptions. ACM SIGARCH Comput. Arch. News 34, 1–17.